DRAM White Papers
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Royal Holloway: Rowhammer – From DRAM faults to escalating privileges
Sponsored by: TechTarget ComputerWeekly.comDiscover how Rowhammer attacks, created from a side effect in dynamic random-access memory (DRAM) that occurs due to increased density, can affect your company's cyber security and how best to protect against them
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MicroScope September Ezine
Sponsored by: MicroScopeFor many, the looming Brexit has stalled IT purchasing all together. But what can your organisation do to counteract this and navigate the complicated matter better than your peers? What does it mean for your employees? Take a look at this article of MicroScope for more information on Brexit's effect on the IT industry.
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New Flash Use Cases Identified and What to Do about the NAND Flash Shortage
Sponsored by: SilkBecause we're in the midst of a worldwide NAND flash shortage, will once-lowered costs now rise? Download this guide as our editors evaluate the impact the NAND flash shortage has on the cost of SSDs (and how that compares per gigabyte to HDDs), as well as new use cases like flash as RAM.
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Future of 3D NAND Technology
Sponsored by: Intel CASTwo new challengers to DRAM's high speed performance – 3DX Point technology and PCM – are running circles around NAND. In this eGuide learn more about them, why analysts predict their longevity for at least 20 years and how vendors are preventing bit rot.
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Dell™Reliable Memory Technology
Sponsored by: DellEMC and Intel®This paper examines the root causes of memory errors and discusses and discusses the core concepts of technology designed to remediate and obviate these errors.
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System Memory Power & Thermal Management in Platforms Built on Intel® Centrino® Duo Mobile Tech
Sponsored by: Intel CorporationThis paper discusses the need for memory throttling and addresses two memory throttling techniques, implemented in platforms built on Intel® Centrino® Duo mobile technology.
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Design-for-Test Analysis of a Buffered SDRAM DIMM
Sponsored by: Texas Instruments, Inc.This document presents a design-for-test analysis of a buffered synchronous dynamic random access memory dual in-line memory module.